In the fast-paced world of technological advancements, the demand for high-speed and error-free wireless communication systems is ever-increasing. From self-driving vehicles to surveillance and tracking systems, the need for reliable data transceivers and radar systems is crucial. One key component that plays a significant role in these systems is the phase-locked loop (PLL), specifically the fractional-N PLL. However, fractional spurs, unwanted signals that degrade performance, have been a persistent issue in many modern radar systems and wireless transceivers. In a groundbreaking study conducted by scientists from Tokyo Tech, two innovative design techniques were proposed to address this problem and pave the way for technological advancements beyond the 5G era.

Fractional-N PLLs are known for their excellent resolution and flexible control of frequency, making them popular choices in various applications. However, jitter and fractional spurs are common enemies that can compromise the performance of these systems. Jitter refers to the deviation from the ideal timing of the synthesized oscillation, while fractional spurs are unwanted signals that arise from errors in the system. Digital-to-time converters (DTCs) are typically used in digital PLLs to counter quantization errors, but imperfections in DTCs, known as integral non-linearities (INLs), often lead to the manifestation of fractional spurs.

The research team from Tokyo Tech, led by Professor Kenichi Okada, introduced two novel design techniques to combat fractional spurs in fractional-N PLLs. The first technique involves the use of a cascaded-fractional divider, where the frequency control word (FCW) is split into two values that are far from an integer. This approach filters out high-frequency components by leveraging the inherent operations of the PLL, without the need for digital pre-distortion (DPD) techniques that can introduce complexity and slow down phase locking. The second technique revolves around a pseudo-differential DTC, which eliminates the trade-offs between power, delay range, noise, and INL in standard DTC implementations. By utilizing two half-range DTCs with the same even-symmetric INLs in a differential operation, the researchers were able to cancel out INLs naturally at the PLL’s phase detector.

The team tested their innovative design techniques by implementing a digital PLL using a 65 nm CMOS process, showcasing a compact active circuit area of only 0.23 mm2. By comparing the performance of their device with existing state-of-the-art designs, the researchers observed significant improvements. The integrated PLL jitter was reduced from 243.5 fs to 143.7 fs by suppressing fractional spurs. Thanks to the cascaded fractional divider and pseudo-differential DTC techniques, the team achieved a new standard of low jitter without the need for DPD technology. This revolutionary approach has the potential to drive technological advancements in various applications where fractional-N PLLs are essential.

The innovative design techniques proposed by the research team from Tokyo Tech offer a promising solution to the longstanding issue of fractional spurs in fractional-N PLLs. By addressing the challenges associated with jitter and unwanted signals, these techniques open doors to enhanced performance in wireless communication, autonomous vehicles, surveillance systems, and beyond. As technology continues to evolve, the development of efficient and reliable communication systems becomes increasingly vital. The future of wireless communication looks brighter than ever with these groundbreaking advancements in PLL design.


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